Copper Sulfate Crystal

Metal Chemicals for FEOL & Advanced Packaging

Product Description

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Table of Contents
1. Executive Summary
1.1 Market Overview
1.2 Technical Trends
2. Scope
3. Introduction
3.1 Damascene/ Interconnect
3.2 Packaging
4. Technology Roadmaps & Limitations
4.1 Damascene
4.2 Packaging
5. Advanced Packaging Technology Background & Trends
5.1 Background
5.2 Market Trends – Advanced Packaging
5.3 Flip Chip Method
5.3.1 Background
5.3.2Advanced Flip Chip
5.4 WLP
5.4.1 Market Trends – WLP
5.5 Wafer Bumping (C4 and C2 Bumps)
5.5.1 Background – Wafer Bumping
5.6 Cu Pillar
5.6.1 Market Trends – Cu Pillar
5.7 Copper Platting Baths
5.7.1 Additives – Cu Plating
5.7.2 Market Trends – Cu Plating
5.7.3 Purity – Cu Plating
5.7.4 Outlook – Cu Plating
6. Equipment Suppliers
7. Copper Plating Supply Chain for Damascene and Packaging
7.1 ASIA Market Activity
7.2 ECD Chemical Demand
8. Sn/Ag/X Solder Application and Market Landscape
8.1 Technical Trends and Applications
8.2 Supply Chain Issues
4.5 Market Landscape
4.6 Technology Trends
10. Solder Bump Market Trends
10.1 Solder Bumps for Advanced WLP
11. UBM
12. TSV

List of Figures
page #
Figure 1 Cross Section Interconnect Damascene Process
Figure 2 Damascene Process
Figure 3 Embedded Memory Examples
Figure 4 Package trends
Figure 5 Packaging Roadmap
Figure 6 Packaging Technology Nodes
Figure 7 Bumping Technology Roadmap
Figure 8 WLP Platforms
Figure 9 Package Scaling
Figure 10 Flip Chip Bump Capacity
Figure 11 FOWLP Forecast (YOLE)
Figure 12 C4 verus C2 Bumps
Figure 13 Why Copper Pillars (Yole)
Figure 14 Mass Reflow vs TC-NCP
Figure 15 LAM/ Novellus Cu Electroplating Chemistry
Figure 16 Typical Electroplating Tank(Novellus)
Figure 17 Wafer Plating Tool
Figure 18 Damasene Plating Equipment Market Share
Figure 19 Packaging Plating Equipment Market Share
Figure 21 Damascene Additives per Year
Figure 22 Packaging Additives per year
Figure 23 SnPB vs SnAgCu Process Window
Figure 24 SAC Solders Ranked by Cost (Indium)
Figure 25 Solder, Cu-Pillars and Bumps (DOW)
Figure 26 Chip Footprint versus I/O count
Figure 27 Bump Wafer Production by Pitch
Figure 28 Mass Reflow(Underfill) vs TC-NDP (Themo-Compression)
Figure 29 Ag/Sn Solder Market Forecast for FOWLP
Figure 30 XRF data for UBM and RDL stacks
Figure 31 Why control bump composition?
Figure 32 TSV Challenges
Figure 33 TSV Process Flow(AMAT)
Figure 34 TSV ECD Chemistry
Figure 35 TSV Processing Cost Comparison

List of Tables

Table 1: Interconnect Technology Trends
Table 2: TSMC & Intel Cu-Pillar Process
Table 3: Cu Pillar Dimension Roadmap
Table 4: Electoplating Chemical Company Market Share
Table 5: Asia Electroplating Chemical Companies Market Share
Table 6: Supplier Profiles Spreadsheet Snippet
Table 7: Chemical Concentration per Company
Table 8: Chemical CAGR
Table 9: Solder Material Cost Analysis
Table 10: Solder Company Ranking

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