450mm And Other Emergency Measures

Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling.

Whether either of these approaches ever materializes is questionable. The cost of developing 450mm or panel-level equipment is enormous, and there has to be enough industry support to provide a reasonable return on investment for enough companies with enough volume. Given the splintering of end markets and consolidation among big chipmakers, this may prove to be more of a rallying cry than reality. In several presentations at SEMI’s Strategic Materials Conference this week, speakers plotted the technical possibility of extending Moore’s Law against the financial impact of continuing Moore’s Law.

The bottom line is that no matter what steps are taken, the price per transistor will increase. As Ben Eynon, senior director for engineering development at Samsung pointed out, even if EUV lithography does become a commercial success, it has a wavelength of 13.5nm. “If we don’t get EUV in quickly, it will go to sub-wavelength right away. Double patterning with EUV isn’t a one-to-one replacement with 193nm immersion, though. Double patterning with immersion is faster than with EUV, which means the price for double patterning with EUV may be higher than quadruple or octuple patterning with immersion. Shooting a drop of molten tin with a high-powered laser also splatters the tin across a very expensive mirror, requiring the mirror to be replaced. And given that 193nm equipment is already fully depreciated, EUV is likely to become a complementary technology to immersion rather than a full replacement.

So where else can the economies of scale associated with node shrinks come from? The answer isn’t clear. One possibility is nowhere, providing there is enough of a performance boost and power reduction to make it worthwhile. Srinivasa Banna, fellow and director of advanced device architecture at GlobalFoundries, said that with new transistor structures there will still be a 10{1c8721459c474d1d5b48ba9ae7120e36de45aa62207fb48292a0a282be55d27f} to 15{1c8721459c474d1d5b48ba9ae7120e36de45aa62207fb48292a0a282be55d27f} performance improvement and a 35{1c8721459c474d1d5b48ba9ae7120e36de45aa62207fb48292a0a282be55d27f} decrease in power. That may be enough to warrant higher prices for chips. Banna noted that more self-aligned features, lower-resistivity interconnects and low-permittivity dielectrics, as well as new device architectures, will be key enablers for continuing Moore’s Law. “We need to optimize resistance,” he said. “That is the innovation of the next 10 years.”

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