Description
This report covers the Metal Chemicals market trends and supply-chain as it applied to Advanced Packaging (wafer level) and Semiconductor Device Manufacturing (damascene process). Included are forecasts for copper plating and additives, market shares, technical trends, and supplier profiles. Also included in the appendix is a supplier product comparison table of publicly available information on plating products used for advanced packaging.
Featured Press Release on Metal Chemicals Market Updates and Report Highlights:
Table of Contents:
Click here for a PDF download of table of contents
1 EXECUTIVE SUMMARY 9 1.1 EXECUTIVE SUMMARY 10 1.2 ADVANCED PACKAGING PER WAFER STARTS 11 1.3 DEVICE DEMAND DRIVERS - LOGIC 12 1.4 CU PLATING FORECAST FOR CU INTERCONNECTS AND ADVANCED PACKAGING 13 1.5 MARKET SHARES 14 1.6 SUPPLIER ACTIVITIES – VARIOUS ANNOUNCEMENTS 15 1.7 RISK FACTORS 16 1.8 ANALYST ASSESSMENT 17 2 SCOPE, PURPOSE AND METHODOLOGY 18 2.1 SCOPE 19 2.2 PURPOSE & METHODOLOGY 20 2.3 OVERVIEW OF OTHER TECHCET CMR REPORTS 21 3 SEMICONDUCTOR INDUSTRY MARKET OUTLOOK 22 3.1 WORLDWIDE ECONOMY AND OVERALL INDUSTRY OUTLOOK 23 3.1.1 SEMICONDUCTOR INDUSTRIES TIES TO THE GLOBAL ECONOMY 25 3.1.2 SEMICONDUCTOR SALES GROWTH 26 3.1.3 TAIWAN OUTSOURCE MANUFACTURER MONTHLY SALES TRENDS 27 3.2 CHIPS SALES BY ELECTRONIC GOODS SEGMENT 28 3.2.1 ELECTRONICS OUTLOOK 29 3.2.2 AUTOMOTIVE INDUSTRY OUTLOOK 30 3.2.3 SMARTPHONE OUTLOOK 33 3.2.4 PC OUTLOOK 34 3.2.5 SERVERS / IT MARKET 35 3.3 SEMICONDUCTOR FABRICATION GROWTH & EXPANSION 36 3.3.1 IN THE MIDST OF HUGE INVESTMENT IN CHIP EXPANSIONS 37 3.3.2 NEW FABS IN THE US 38 3.3.3 WW FAB EXPANSION DRIVING GROWTH 39 3.3.4 EQUIPMENT SPENDING TRENDS 40 3.3.5 ADVANCED LOGIC TECHNOLOGY ROADMAPS 41 3.3.6 FAB INVESTMENT ASSESSMENT 44 3.4 POLICY & TRADE TRENDS AND IMPACT 45 3.5 SEMICONDUCTOR MATERIALS OVERVIEW 46 3.5.1 TECHCET WAFER STARTS FORECAST THROUGH 2028 47 3.5.2 TECHCET MATERIALS MARKET FORECAST THROUGH 2028 48 4 METAL CHEMICALS MARKET BY SEGMENT 49 4.1 DEFINITIONS 50 4.2 METAL PLATING CHEMICALS MARKET OVERVIEW 52 4.2.1 OVERVIEW – CU ADVANCED PACKAGING AND CHIP INTERCONNECTS METALLIZATION 53 4.2.2 OVERVIEW - PLATING MARKET TRANSITIONAL TRENDS 54 4.3 ADVANCED PACKAGING METALLIZATION – MARKET DRIVERS 55 4.3.1 ADVANCED PACKAGING - ADDITIVES FOR CU PLATING REVENUE 56 4.3.2 ADVANCED PACKAGING – COPPER CHEMICALS REVENUE 57 4.3.3 ADVANCED PACKAGING ADDITIVE VOLUMES 58 4.3.4 OTHER PLATING MATERIALS FOR ADVANCED PACKAGING 59 4.3.5 SN / SNAG PLATING 60 4.4 CHIP INTERCONNECTS GROWTH TRENDS 62 4.4.1 CHIP INTERCONNECTS GROWTH DRIVERS 63 4.4.2 CHIP INTERCONNECTS CU PLATING REVENUES 64 4.4.3 CHIP INTERCONNECTS ADDITIVE VOLUMES 65 4.5 MINE LOCATIONS FOR METALS IN PLATING CHEMICALS 66 4.6 POSSIBLE CHOKE POINTS FOR METALS USED IN IC PLATING 67 4.7 FUTURE POSSIBLE DEMAND PRICE PRESSURES 68 5 TECHNICAL TRENDS 69 5.1 CHEMISTRIES USE FOR SEMICONDUCTOR METAL PLATING 70 5.2 PACKAGING TECH TRENDS 71 5.2.1 PACKAGING TECHNICAL CHALLENGES 72 5.3 TECH TRENDS 73 5.3.1 MARKET DRIVES TECHNOLOGY TRENDS 74 5.3.2 ADV LOGIC INTERCONNECT WIRING TECHNOLOGY EVOLUTION 75 5.3.3 CU INTERCONNECTS QUALIFICATION REQUIREMENTS 77 5.3.4 LOGIC METALLIZATION ROADMAP 78 5.3.5 ADV LOGIC BURIED POWER RAIL 80 5.3.6 TECHNOLOGY ROADMAP: DRAM WITH MO OR RU 81 5.3.7 PRECURSOR TECHNOLOGY ROADMAP: 3D NAND USING MO OR RU 83 5.3.8 EXAMPLE OF LOGIC PRO CESS FLOW 20 NM TO 32 NM LOGIC PVD 85 5.3.9 TECHNICAL REQUIREMENTS SUMMARY 1/2 86 6 COMPETITIVE LANDSCAPE 88 6.1 TOTAL ADVANCED PACKAGING AND INTERCONNECTS MARKET SHARES 89 6.2 OEM MARKET SHARE – PLATING EQUIPMENT 90 6.3 MARKET SHARE BY APPLICATION – CU PLATING FOR ADVANCED PACKAGING 91 6.4 REGIONAL PLAYERS AND OTHERS 92 6.5 M&A ACTIVITY 93 7 ANALYST ASSESSMENT 94 7.1 ADVANCED METAL PLATING APPLICATIONS MARKET ASSESSMENT 95 8 SUPPLIER PROFILES 96 BASF DUPONT CHANG CHUN GROUP INCHEON CHEMICAL COMPANY ISHIHARA CHEMICAL/UNICON ...AND 9 MORE 9 APPENDIX A: PACKAGING TECH TRENDS 160 9.1 TECHNOLOGY CHALLENGE 161 9.1.1 METAL CLEANINGS CHALLENGE 162 9.1.2 MARKET DYNAMIC 163 9.1.3 WAFER LEVEL PLATING-FIRST LEVEL INTERCONNECT 164 9.1.4 MARKET DRIVERS OF ADVANCED PACKAGING APPLICATIONS 165 9.1.5 WAFER LEVEL PACKAGING ARCHITECTURES 166 9.1.6 TECH TRENDS- RDL 167 9.1.7 MARKET DRIVERS OF CHIPLET ARCHITECTURE 169 9.1.8 TSV FILLING 2.5-3D 172 9.1.9 PACKAGING ELECTROPLATING REQUIREMENTS 173 List of Figures FIGURE 1.1: PLATING MATERIALS FOR ADVANCED PACKAGING AND INTERCONNECT REVENUES ($M’S) 10 FIGURE 1.2. WAFERS/YR & % OF PACKAGING THAT IS ADVANCED PACKAGING (AP) 11 FIGURE 1.3: ADV LOGIC DEVICE GROWTH FORECAST 12 FIGURE 1.4: COPPER PLATING CHEMICALS REVENUES ($M’S) FOR ADVANCED PACKAGING & FE CU INTERCONNECTS 13 FIGURE 1.5: 2023 SUPPLIER MARKET SHARES CU PLATING FOR INTERCONNECT ADDITIVES 14 FIGURE 1.6: 2023 SUPPLIER MARKET SHARES CU PLATING FOR ADV. PACKAGING 14 FIGURE 3.1: GLOBAL ECONOMY AND THE ELECTRONICS SUPPLY CHAIN (2023) 25 FIGURE 3.2: WORLDWIDE SEMICONDUCTOR SALES 26 FIGURE 3.3: TECHCET’S TAIWAN SEMICONDUCTOR INDUSTRY INDEX (TTSII) IN 000’S OF NTD 27 FIGURE 3.4: 2023 SEMICONDUCTOR CHIP APPLICATIONS 28 FIGURE 3.5: GLOBAL LIGHT VEHICLE UNIT SALES 30 FIGURE 3.6: ELECTRIFICATION TREND BY WORLD REGION 31 FIGURE 3.7: AUTOMOTIVE SEMICONDUCTOR PRODUCTION 37 FIGURE 3.8: MOBILE PHONE SHIPMENTS, WW ESTIMATES 32 FIGURE 3.9: WORLDWIDE PC AND TABLET FORECAST 33 FIGURE 3.9: WORLDWIDE PC AND TABLET FORECAST 34 FIGURE 3.10: TSMC PHOENIX CAMPUS WITH THE 2ND FAB VISIBLE IN THE BACKGROUND 36 FIGURE 3.11: ESTIMATED GLOBAL FAB SPENDING 2023-2028 37 FIGURE 3.12: FAB EXPANSIONS WITHIN THE US 38 FIGURE 3.13: SEMICONDUCTOR CHIP MANUFACTURING REGIONS OF THE WORLD 39 FIGURE 3.14: GLOBAL TOTAL EQUIPMENT SPENDING (US$ M) AND Y-O-Y CHANGE 30 FIGURE 3.15: ADVANCED LOGIC DEVICE TECHNOLOGY ROADMAP OVERVIEW 41 FIGURE 3.16: DRAM TECHNOLOGY ROADMAP OVERVIEW 42 FIGURE 3.17: 3D NAND TECHNOLOGY ROADMAP OVERVIEW 43 FIGURE 3.18: INTEL OHIO PLANT SITE AS OF FEB. 2024 44 FIGURE 3.19: TECHCET WAFER START FORECAST BY NODE SEGMENTS 47 FIGURE 3.20: TECHCET WORLDWIDE MATERIALS FORECAST ($M USD) 48 FIGURE 4.1: PACKAGING METALLIZATION APPLICATIONS 50 FIGURE 4.2: USE OF SILICON INTERPOSER IN 2.5D PACKAGING 51 FIGURE 4.3: VERSIONS OF TSV & PROCESS FLOW EXAMPLE 51 FIGURE 4.4: PLATING MATERIALS FOR ADVANCED PACKAGING AND DEVICE INTERCONNECT REVENUES (M’S) 52 FIGURE 4.5: CU PLATING CHEMICALS 5-YEAR FORECAST 53 FIGURE 4.6: WAFERS/YR & % OF PACKAGING THAT IS ADVANCED PACKAGING 55 FIGURE 4.7: REVENUE FORECAST CU PLATING ADVANCED PACKAGING 56 FIGURE 4.8: CU PILLAR & CU RDL SEGMENTED FORECAST 57 FIGURE 4.9: ADV. PACKAGING CU CUSO4 AMOUNT DEMAND FORECAST 58 FIGURE 4.10: ADV. PACKAGING CU/VMS VOLUME DEMAND FORECAST ADV.PACKAGING CU PLATING ADDITIVES 58 FIGURE 4.11: BUMPING MATERIALS FOR FIRST LEVEL INTERCONNECT 59 FIGURE 4.12: HYBRID BONDING PROCESS 59 FIGURE 4.13: SN AND SNAG PLATING REVENUE 60 FIGURE 4.14: NICKEL PLATING REVENUE 61 FIGURE 4.15: ADV LOGIC DEVICE GROWTH FORECAST 62 FIGURE 4.16: METAL PLATING WAFER PASSES 63 FIGURE 4.17: WW DAMASCENE REVENUE FORECAST ESTIMATES 64 FIGURE 4.18: DAMASCENE CUSO4 VOLUME DEMAND FORECAST 65 FIGURE 4.19: DAMASCENE CU PLATING CHEMICAL AMOUNT DEMAND FORECAST 65 FIGURE 5.1: KEY TRENDS IN ADVANCED PACKAGING 71 FIGURE 5.2: CHALLENGES OF ELECTROPLATING VIA FILL 72 FIGURE 5.3: METAL INTERCONNECTS BY LOGIC NODE 74 FIGURE 5.4: INTERCONNECT METAL COMPARISON BY RESISTIVITY 75 FIGURE 5.5: CU CHIP INTERCONNECTS QUALIFICATION 77 FIGURE 5.6: LEADING EDGE LOGIC POWER RAIL SCHEMES 80 FIGURE 5.7: DRAM STRUCTURE 81 FIGURE 5.8: 3D NAND STRUCTURE 83 FIGURE 6.1: TOTAL PLATING FOR ADV. PACKAGING AND CU INTERCONNECT ADDITIVES 2023 89 FIGURE 6.2: PLATING EQUIPMENT OEM MARKET SHARES % 2023 90 FIGURE 6.3: PLATING CHEMICAL SUPPLIER FOR INTERCONNECTS AND ADVANCED PACKAGING APPLICATIONS 91 FIGURE 9.1: CLEANING COMPLEXITY 160 FIGURE 9.2: OSATS PACKAGING BUSINESS CANNIBALIZATION TREND 162 FIGURE 9.3: WAFER LEVEL PLATING 163 FIGURE 9.4: ADVANCED PACKAGING MARKET DRIVERS AND APPLICATIONS 164 FIGURE 9.4: ADVANCED PACKAGING MARKET DRIVERS AND APPLICATIONS 165 FIGURE 9.5: FAN-IN (WLCSP) & FAN-OUT (WLFO) COMPARISON 166 FIGURE 9.6: RDL CIRCUITRY EXAMPLE 167 FIGURE 9.7: COMPARISON WITH DAMASCENE- TYPE RDL 168 FIGURE 9.8: COST/PERFORMANCE IMPROVEMENTS THROUGH CHIPLETS INTEGRATION 169 FIGURE 9.9: 2.5 AND 3D PACKAGING EXAMPLES 170 FIGURE 9.10: USE OF SILICON INTERPOSER 171 FIGURE 9.11: TSV PROCESS FLOW EXAMPLE 172 FIGURE 9.12: PROCESS COMPARISON OF TRADITIONAL VS. WLP FLOWS 173 List of Tables TABLE 3.2: BATTERY ELECTRIC VEHICLE (BEV) REGIONAL TRENDS 36 TABLE 3.3: DATA CENTER SYSTEMS AND COMMUNICATION SERVICES MARKET SPENDING 2023 40 TABLE 5.1: IRDS 2023 MORE MOORE INTERCONNECT ROADMAP 76 TABLE 5.2: BARRIER METAL ROADMAP 78 TABLE 5.3: METALS REQUIRED FOR DEVICE FEATURES 79 TABLE 5.4: DRAM USE OF MO OR RU PRESENT & FUTURE 81 TABLE 5.5: GENERAL PROCESS FLOW ADVANCED DRAM 82 TABLE 5.5: 3D NAND MATERIAL CHANGES PRESENT & FUTURE 83 TABLE 5.6: NUMBER OF STACKS (S) & LAYERS (L) PER GENERATION OF 3DNAND – SOME ARE ESTIMATES FOR THE FUTURE 84 TABLE 5.7: EXAMPLE OF LOGIC PROCESS FLOW 20 NM TO 32 NM LOGIC PVD 85 TABLE 5.8: TECHNICAL REQUIREMENTS SUMMARY 86 TABLE 5.9: TECHNICAL REQUIREMENTS SUMMARY, CONTINUED 87 TABLE 6.1: REGIONAL PLAYERS – MARKET LEADER AND “OTHERS” 92 TABLE 9.1: CU PACKAGING APPLICATIONS AND REQUIREMENTS 174
