Growth Driven by Advanced Logic Nodes and Advance Packaging
San Diego, CA, April 3, 2024: TECHCET — the advisory firm providing materials market information for semiconductor supply chain resilience — is forecasting Metal Plating Chemicals to grow 7% in 2024, to reach over $1 billion. This is a significant jump from the -6% dip to $947 million in 2023. The Compound Average Growth Rate for these metal plating chemicals is expected to exceed 5.4% through 2023-2028. Growth drivers include increased use in advanced packaging, such as redistribution layers (RDL) and copper pillar structures, and higher layer counts in next generation logic devices, soon to be followed with buried power rails and backside copper wiring, as highlighted in TECHCET’s Critical Materials Report™ on Metal Chemicals.
TECHCET believes the first quarter of 2024 will continue to see slow growth in semiconductor device production, followed by steady improvement through the remainder of 2024. In 2H2024, higher device demand is expected due to growth of numerous applications (electric cars, more fast charging stations, AI, more data storage, etc.) in combination with the US CHIPS Act and similar investments by Europe, Japan, and China. These will drive an increase in demand for metal interconnect layers and more advanced packaging materials.
Advanced Packaging requirements continue to be driven by increases in Wafer Level Packaging (WLP), including Fanout WLP (FOWLP) packaging. In advanced packaging for high-performance devices, there is increased need for RDL, interposers, and silicon bridge technology. Heterogenous integration, embedded multi-die interconnect bridge (EMIB), Chiplets, and power devices are expected to challenge the plating requirements in terms of quality of material being deposited.
TECHCET does not expect new players in the plating chemicals market and is following the introduction of ruthenium or molybdenum to possibly displace the tantalum and cobalt barrier layer at the GAA nodes. Ruthenium or molybdenum (ALD or CVD, not plating) will possibly fill the interconnects & vias between Metal 0 (M0) to Metal 2 (M2) interconnect layers for Advanced Logic. Wafer backside power wiring, using buried power rail contacts to the transistors, will add copper plating volumes to the process, thus leading to more copper plating, even as these replace copper plating at the M8-M14 layers.
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ABOUT TECHCET: TECHCET CA LLC is an advisory services firm expert in market and supply-chain analysis of electronic materials for the semiconductor, display, solar/PV, and LED industries. TECHCET offers consulting, subscription service, and reports, including the Critical Materials Council (CMC) of semiconductor fabricators and Data Subscription Service (DSS). For additional information, please email us here, call +1-480-332-8336, or go to www.techcet.com.