By Karey Holland, Ph.D., TECHCET
The 2023 ALD/ALE Conference in Bellevue, WA, which was just completed July 26, featured new research on ALD/ALE processes. Key areas of interest were (1) ALD of materials for emerging semiconductor devices, (2) ALE for challenges structures, and (3) precursors for metal oxide EUV negative tone photoresists. The conference also covered areas related to solar cells, nanoparticles, thermal and others on plasma, and other applications.
Prof. M. Leskela at University Helsinki gave the ALD Keynote presentation reviewing the history of ALD (ALD was “invented” in 1976) and how it has evolved. He elaborated on how ALD began as forming a perfect mono-layer by mono-layer, defect-free film deposition, to focus on conformality, defect corrections, and “reverse” ALD – which is ALE. He also explained the interesting area-selective (AS) ALD and how this is particularly helpful with the constantly shrinking dimensions of advanced ICs. AS ALD is particularly interesting for device fabrications – a precursor may attach to a surface with one material, but not to other parts with a different material. An example is acetylacetonate – it allows selective deposition of SiO2 on GeO, SiNx, SiO2, and WO3, with no deposition on Al2O3, TiO2, and HfO2. Also, for ALD fill of holes where bottom-up deposition is preferred, this can be achieved by capillary condensation, which is very helpful in filling narrow, deep features with metals. Leskela noted that there is more to come on these developments.
The ALE Keynote Presentation was given by Tristan Tronic, Ph.D. of Intel. Tronic focused on the need for ALE with the ever-shrinking advanced device dimensions. ALE is particularly helpful as it can be set up to selectively etch a range of dielectrics‚ semiconductors‚ and conductors. Tronic focused on how ALE can facilitate the advancing nodes, starting with GAA horizontal nano-ribbon devices – a critical new transistor that Samsung says they already have in risk production, and that Intel and TSMC plan to produce soon. The process flow for these GAA is quite interesting – it starts with 5nm epi layers of Si and SiGe on top of the wafer, patterned to produce the transistor area, followed by SiGe being removed to produce open areas around parts of the Si nano-ribbons. These nano-ribbons must then be coated on all sides with dielectric (gate dielectrics) and then metals (gate electrodes). ALE etch removal of the SiGe and selective ALD of the deposited materials adds much greater control to the processes. From GAA, the next step is expected to stack the nFET or pFET GAA on top of the alternative FET GAA transistors. This will require even more control of depositions and etches in very small features. The presentation included very interesting process challenges for the backside power rail (BPR) that will reduce the number of copper interconnects on the top of the chip, but require connection to the bottom of the wafer where several copper wiring levels will be fabricated.
Other interesting talks include David Thompson of Applied Materials presenting on how we are moving ALD and ALE from R&D to high-volume semiconductor device manufacturing. In particular, selective ALD and ALE can have important improvements such as possibly reducing process steps for advanced technology nodes. However, ALD and ALE also have some challenges as we integrate these processes into the fabs.
In the ALE metals session, a presentation was made of a wet ALE, at atmospheric pressure (not done in a vacuum chamber). With the correct chemicals, it is certainly possible to get monolayers of materials to attach to a specific material, react with it, and then be removed by liquid solvents. However, many of us found this intriguing, as ALD and ALE are usually considered low pressure processes.
The 2D ALD was particularly interesting as it covered the metal dichalcogenides (MDCs) which are a class of MX2 compounds (M=metal) being evaluated for the 2D transistors of the future.
The conference’s content on ALD for photolithography also provided intriguing insights and research. In today’s advanced node device manufacturing, we increasingly use the EUV (13nm) lithography technology. EUV photoresists can be positive tone (what is exposed is removed by the developer) or negative tone (what is not exposed is removed by the developer). The metal-oxide (MOX) negative tone photoresists are gaining traction in the semiconductor industry. One version of MOX is a traditional liquid spin-on photoresist with wet development. As an alternative, Lam Research (teamed up with Gelest and Entegris) has shown interesting performance by using ALD MOXs. At the conference, Prof. J. Kim (UT Dallas) presented a detailed paper on ALD of organic-inorganic hybrid photoresists. He focused on trimethylaluminum (TMA) and hydroquinone (HQ) that creates alumina where exposed with low-energy electron beam (to mimic EUV). Several presentations after Prof. Kim’s also reviewed other versions of MOX, including leaving HfOx, ZrOx, and other metal oxides on the wafers after exposure. The current MOX that’s been presented by Lam Research at the Critical Materials Council Conference is based on SnOx.
The ALD/ALE conference was an excellent opportunity to learn of new materials and processes for the advancing semiconductor industry, and TECHCET plans to continue monitoring such developments as they make their way into the market.
ABOUT TECHCET: TECHCET CA LLC is an advisory services firm expert in market and supply-chain analysis of electronic materials for the semiconductor, display, solar/PV, and LED industries. TECHCET offers consulting, subscription service, and reports, including the Critical Materials Council (CMC) of semiconductor fabricators and Data Subscription Service (DSS). For additional information, please contact firstname.lastname@example.org, +1-480-332-8336, or go to www.techcet.com.